1. Field of the Invention
The present invention relates to a field effect transistor (FET), particularly a MOSFET, well adapted for increases in the densities and speeds of integrated circuits, and a process for producing the same.
2. Prior Art
A brief description will first be made of the structure of a well known conventional MOSFET.
FIG. 1 is a schematic cross-sectional view of a typical example of the structure of a conventional MOSFET, the cross section of which is drawn along the length-wise direction of a channel and perpendicular to the surface of a substrate. As is well known, this MOSFET is produced according to the following procedure. A field oxide film 12 and an inner oxide film 14 in a respective zone surrounded by the field oxide film 12 are formed through thermal oxidation of a silicon substrate 10 of a certain conductivity type. The whole surface of the oxide film 14 is then covered with a gate electrode metal according to a CVD method. The deposited gate electrode metal is patterned according to a photolithographic etching technology to form a gate electrode 16. The oxide film beneath the gate electrode 16 is to serve as a gate oxide film 18, as is well known. Using this gate electrode 16 as a mask, ion implantation of a suitable impurity is effected, followed by thermal diffusion of the implanted impurity ions to form first and second principal electrode regions (source/drain regions) 20 and 22. Contact holes are formed through the oxide film 14 (that may include an intermediate insulating film in the case where it is provided), followed by formation of first and second principal electrodes (source/drain electrodes) 24 and 26.
In the conventional structure of such a FET produced in the foregoing manner, however, the following problems in particular arise when the gate length is decreased in keeping with the increasing scale of integration and speed of an integrated circuit.
The first problem is a liability to a short channel effect.
The second problem is a liability to a punch through effect.
The third problem is increased influences on the characteristics of the device despite of a decreased junction capacitance in junctions between first and second principal electrode regions and a silicon substrate.
One solution to the first and second problems is a method of forming an LDD (lightly doped drain-source) structure in a semiconductor device. In the LDD structure, however, the electric resistance of the principal electrode regions (source/drain regions) is increased. Furthermore, when an attempt is made to solve the foregoing three problems and lower the electric resistance of the principal electrode regions, a difficulty is encountered in dimensional control in the course of production of a device.
An SOI (semiconductor on insulator) structure was proposed as a solution to the above-mentioned third problem. In this structure, the junction capacitance can be decreased, but a difficulty is encountered in forming the SOI structure itself.
An object of the present invention is to provide a field effect transistor having a structure wherein manifestation of the above-mentioned short channel effect and punch through effect can be suppressed as much as possible and the influence of the junction capacitance on the characteristics of the device can be suppressed as much as possible, while at the same time setting the electric resistance of the principal electrode regions thereof at a low level, and a process for producing the same.